Design of a QPSK/16 QAM LMDS downstream receiver ASIC chip

This paper presents a QPSK/16 QAM LMDS (local multipoint distribution services) downstream receiver ASIC chip. The proposed LMDS chip consists of a blind equalizer, a timing recovery block and a carrier recovery block. The blind equalizer uses a DFE (decision feedback equalizer) structure using CMA (constant modulus algorithm). The symbol timing recovery uses the modified parabolic interpolator and the decision-directed carrier recovery is used to remove the carrier frequency offset, phase offset and phase jitter. The implemented LMDS receiver can support four data rates, 10, 20, 30 and 40 Mbps and can accommodate the symbol rate up to 10 Mbaud. This symbol rate is faster than existing QAM receivers.

[1]  H. Samueli,et al.  A 70 Mb/s variable-rate 1024-QAM cable receiver IC with integrated 10 b ADC and FEC decoder , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[2]  Lars Erup,et al.  Interpolation in digital modems. II. Implementation and performance , 1993, IEEE Trans. Commun..

[3]  Babak Daneshrad,et al.  A VLSI architecture for a single-chip 5-Mbaud QAM receiver , 1992, [Conference Record] GLOBECOM '92 - Communications for Global Users: IEEE.

[4]  Floyd M. Gardner,et al.  A BPSK/QPSK Timing-Error Detector for Sampled Receivers , 1986, IEEE Trans. Commun..

[5]  Muh-Tian Shiue,et al.  A VLSI Architecture Design for Dual-Made QAM and VSB Digital CATV Transceiver , 1998 .

[6]  João Cesar M. Mota,et al.  A predictive constant modulus algorithm for blind equalization in QAM systems , 1997, Proceedings of ICC'97 - International Conference on Communications.

[7]  H. Samueli,et al.  A 200-MHz all-digital QAM modulator and demodulator in 1.2- mu m CMOS for digital radio applications , 1991 .

[8]  D. D. Falconer,et al.  Jointly adaptive equalization and carrier recovery in two-dimensional digital communication systems , 1976, The Bell System Technical Journal.