Disturb-free 5T loadless SRAM cell design with multi-vth transistors using 28 nm CMOS process

A single-ended load SRAM cell composed of multi-Vth transistors is proposed in this study. Particularly, the PDP (power-delay product) performance of the loadless SRAM cell is enhanced by a write assistant loop and an isolated wordline-controlled transistor (WLC). Additionally, a shared bitline inverter is added on the column-wise bitline to boost the read access speed at the minimal expense of area cost. The energy dissipation per write/read operation is found to be 96.624/8.104 fJ provided that the SRAM cells is driven a 0.8 V VDD power supply using a typical 28 nm CMOS technology.

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