Implementing Neon: a 256-bit graphics accelerator

High-performance 3D graphics accelerators traditionally require multiple chips on multiple boards. In contrast, Neon-a single chip-performs like a multichip design, accelerating openGL 3D rendering and X11 and windows/NT 2D rendering.

[1]  Christopher W. Fraser,et al.  A Retargetable C Compiler: Design and Implementation , 1995 .

[2]  Juan Pineda,et al.  A parallel algorithm for polygon rasterization , 1988, SIGGRAPH.

[3]  Robert Ulichney.  One-dimensional dithering , 1998, Other Conferences.

[4]  Z.S. Hakura,et al.  The Design And Analysis Of A Cache Architecture For Texture Mapping , 1997, Conference Proceedings. The 24th Annual International Symposium on Computer Architecture.

[5]  Robert Ulichney,et al.  Window-Extent Tradeoffs in Inverse Dithering , 1998, Color Imaging Conference.

[6]  A. C. Barkans,et al.  Color Recovery: True-Color 8-Bit Interactive Graphics , 1997, IEEE Computer Graphics and Applications.