Test data compression using dictionaries with fixed-length indices [SOC testing]
暂无分享,去创建一个
[1] Janak H. Patel,et al. A case study on the implementation of the Illinois Scan Architecture , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[2] Brion L. Keller,et al. OPMISR: the foundation for compressed ATPG vectors , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[3] A.H. El-Maleh,et al. Extended frequency-directed run-length code with improved application to system-on-a-chip test data compression , 2002, 9th International Conference on Electronics, Circuits and Systems.
[4] Ajay Khoche,et al. Packet-based input test data compression techniques , 2002, Proceedings. International Test Conference.
[5] Nilanjan Mukherjee,et al. Embedded deterministic test for low cost manufacturing test , 2002, Proceedings. International Test Conference.
[6] Nur A. Touba,et al. Test vector decompression via cyclical scan chains and its application to testing core-based designs , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[7] Bashir M. Al-Hashimi,et al. Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression , 2002, DATE.
[8] Janak H. Patel,et al. Test set compaction algorithms for combinational circuits , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).
[9] Hans-Joachim Wunderlich,et al. RESPIN++ - deterministic embedded test , 2002, Proceedings The Seventh IEEE European Test Workshop.
[10] David Salomon,et al. Data Compression: The Complete Reference , 2006 .
[11] Krishnendu Chakrabarty,et al. Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.
[12] Aiman H. El-Maleh,et al. A geometric-primitives-based compression scheme for testing systems-on-a-chip , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.
[13] Krishnendu Chakrabarty,et al. System-on-a-chip test-data compression and decompressionarchitectures based on Golomb codes , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[14] Christos A. Papachristou,et al. Multiscan-based test compression and hardware decompression using LZ77 , 2002, Proceedings. International Test Conference.
[16] H. Wunderlich,et al. Bit-flipping BIST , 1996, ICCAD 1996.
[17] Alex Orailoglu,et al. Test volume and application time reduction through scan chain concealment , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[18] Alex Orailoglu,et al. Reducing test application time through test data mutation encoding , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[19] G. G. Stokes. "J." , 1890, The New Yale Book of Quotations.
[20] David S. Johnson,et al. Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .
[21] Nur A. Touba,et al. Altering a pseudo-random bit sequence for scan-based BIST , 1996, Proceedings International Test Conference 1996. Test and Design Validity.
[22] Huaguo Liang,et al. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters , 2001, J. Electron. Test..
[23] Brion L. Keller,et al. A SmartBIST variant with guaranteed encoding , 2001, Proceedings 10th Asian Test Symposium.
[24] R. K. Shyamasundar,et al. Introduction to algorithms , 1996 .
[25] Harald P. E. Vranken,et al. Enhanced Reduced Pin-Count Test for Full-Scan Design , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[26] Krishnendu Chakrabarty,et al. Deterministic Built-in Pattern Generation for Sequential Circuits , 1999, J. Electron. Test..
[27] Irith Pomeranz,et al. On test data volume reduction for multiple scan chain designs , 2003, TODE.
[28] P. T. Gonciari,et al. Improving compression ratio, area overhead, and test application time for system-on-a-chip test data compression/decompression , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[29] Nur A. Touba,et al. Scan vector compression/decompression using statistical coding , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).