Evolution of NAND Flash Memory: From 2D to 3D as a Storage Market Leader

NAND flash memory is evolving from 2D to 3D structure since 2D NAND flash faced its limitation of size reduction. In this paper, the limitations of 2D planar technology and the development history of 3D NAND flash will be reviewed. Finally, we will discuss the problems to overcome in order to succeed the development of 3D NAND flash.

[1]  Kinam Kim,et al.  Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node , 2006, 2006 International Electron Devices Meeting.

[2]  Krishna Parat,et al.  25nm 64Gb MLC NAND technology and scaling challenges invited paper , 2010, 2010 International Electron Devices Meeting.

[3]  Shinsugita-cho Isogo-ku,et al.  Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory , 2007 .

[4]  Jonghoon Park,et al.  11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

[5]  Junhee Lim,et al.  A new ruler on the storage market: 3D-NAND flash for high-density memory and its technology evolutions and challenges on the future , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[6]  Jangho Park,et al.  Integration Technology of 30nm Generation Multi-Level NAND Flash for 64Gb NAND Flash Memory , 2007, 2007 IEEE Symposium on VLSI Technology.

[7]  Jeong-Don Ihm,et al.  256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers , 2017, IEEE Journal of Solid-State Circuits.

[8]  Won-Tae Kim,et al.  19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[9]  Yeong-Taek Lee,et al.  A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories , 2008, IEEE Journal of Solid-State Circuits.

[10]  Dong Woo Kim,et al.  Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory , 2006, 2009 Symposium on VLSI Technology.

[11]  Wook-Ghee Hahn,et al.  A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate , 2016, IEEE Journal of Solid-State Circuits.