论文信息 - Optimization of Reversible Circuits Using Gate Pair Classification - 字舞流文

Optimization of Reversible Circuits Using Gate Pair Classification

Chetan Vudadha | M. B. Srinivas | P. Sai Phaneendra | M. Srinivas | P. Phaneendra | C. Vudadha

[1] Reversible Computation , 2013, Lecture Notes in Computer Science.

[2] Mathias Soeken,et al. White Dots do Matter: Rewriting Reversible Logic Circuits , 2013, RC.

[3] Robert Wille,et al. Improving ESOP-Based Synthesis of Reversible Logic Using Evolutionary Algorithms , 2011, EvoApplications.

[4] Charles H. Bennett,et al. Logical reversibility of computation , 1973 .

[5] Kamalika Datta,et al. An ESOP-Based Reversible Circuit Synthesis Flow Using Simulated Annealing , 2014, ACSS.

[6] Giovanni De Micheli,et al. Hierarchical reversible logic synthesis using LUTs , 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

[7] Robert Wille,et al. Reducing the number of lines in reversible circuits , 2010, Design Automation Conference.

[8] Rolf Drechsler,et al. Improved Cube List Based Cube Pairing Approach for Synthesis of ESOP Based Reversible Logic , 2014, Trans. Comput. Sci..

[9] Robert Wille,et al. Towards a Design Flow for Reversible Logic , 2010 .

[10] Igor L. Markov,et al. Synthesis and optimization of reversible circuits—a survey , 2011, CSUR.

[11] Gerhard W. Dueck,et al. Techniques for the synthesis of reversible Toffoli networks , 2006, TODE.