Design and Optimization of Nonvolatile Multibit 1 T 1 R Resistive RAM

Memristor-based random access memory (RAM) is being explored as a potential replacement for flash memory to sustain the historic trends in the improvement of density, access time, and energy consumption of nonvolatile memory. In this paper, we present the detailed functionality of multibit one-transistor one-memristor (1T1R) cell-based memory arrays, and propose circuit-level performance and energy models for an individual memory cell and the memory array as a whole. We consider titanium dioxide (TiO2)and hafnium oxide (HfOx )based memristors, and for these technologies, there is a sub-10% difference between energy and performance computed using our models and HSPICE simulations. Using a performance-driven design approach, the energy-optimized TiO2-based resistive RAM (RRAM) array consumes the least write (4.06 pJ/b) and read energy (188 fJ/b) when storing 3 b/cell for 100-ns write and 1-ns read access times. Similarly, HfOx -based RRAM array consumes the least write (365 fJ/b) and read energy (173 fJ/b) when storing 3 b/cell for 1-ns write and 200-ns read access times. We also present a detailed analysis of the implications of process, voltage, and temperature variations on the performance and energy consumption of a multibit RRAM cell.

[1]  Dmitri B. Strukov,et al.  Intrinsic constrains on thermally-assisted memristive switching , 2011 .

[2]  Kyoung-Rok Cho,et al.  Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Dalibor Biolek,et al.  SPICE Model of Memristor with Nonlinear Dopant Drift , 2009 .

[4]  Garrett S. Rose,et al.  A read-monitored write circuit for 1T1M multi-level memristor memories , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[5]  Shimeng Yu,et al.  On the Switching Parameter Variation of Metal Oxide RRAM—Part II: Model Corroboration and Device Design Strategy , 2012, IEEE Transactions on Electron Devices.

[6]  K. J. Kuhn,et al.  Considerations for Ultimate CMOS Scaling , 2012, IEEE Transactions on Electron Devices.

[7]  Anantha Chandrakasan,et al.  A low-voltage 1Mb FeRAM in 0.13μm CMOS featuring time-to-digital sensing for expanded operating margin in scaled CMOS , 2011, 2011 IEEE International Solid-State Circuits Conference.

[8]  E. Sail,et al.  A multiplexer based decoder for flash analog-to-digital converters , 2004, 2004 IEEE Region 10 Conference TENCON 2004..

[9]  Stephen J. Wolf,et al.  The elusive memristor: properties of basic electrical circuits , 2008, 0807.3994.

[10]  Ki-Whan Song,et al.  A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW , 2011, 2011 IEEE International Solid-State Circuits Conference.

[11]  Shimeng Yu,et al.  On the Variability of HfOx RRAM: From Numerical Simulation to Compact Modeling , 2012 .

[12]  Meng-Fan Chang,et al.  Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications , 2012, IEEE Journal of Solid-State Circuits.

[13]  Massimo Rossini,et al.  A 3bit/cell 32Gb NAND flash memory at 34nm with 6MB/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13MB/s , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[14]  D. Batas,et al.  A Memristor SPICE Implementation and a New Approach for Magnetic Flux-Controlled Memristor Modeling , 2011, IEEE Transactions on Nanotechnology.

[15]  Shimeng Yu,et al.  On the Switching Parameter Variation of Metal-Oxide RRAM—Part I: Physical Modeling and Simulation Methodology , 2012, IEEE Transactions on Electron Devices.

[16]  Frederick T. Chen,et al.  Highly scalable hafnium oxide memory with improvements of resistive distribution and read disturb immunity , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[17]  Hai Helen Li,et al.  Spintronic Memristor Through Spin-Torque-Induced Magnetization Motion , 2009, IEEE Electron Device Letters.

[18]  Eisse Mensink,et al.  A Low-Offset Double-Tail Latch-Type Voltage Sense Amplifier , 2007 .

[19]  Yang Xiao,et al.  Low power memristor-based ReRAM design with Error Correcting Code , 2012, 17th Asia and South Pacific Design Automation Conference.

[20]  W. Lu,et al.  High-density Crossbar Arrays Based on a Si Memristive System , 2008 .

[21]  Wei Zhang,et al.  A Look Up Table design with 3D bipolar RRAMs , 2012, 17th Asia and South Pacific Design Automation Conference.

[22]  Ching-Te Chuang,et al.  High-performance SRAM in nanoscale CMOS: Design challenges and techniques , 2007, 2007 IEEE International Workshop on Memory Technology, Design and Testing.

[23]  Leon O. Chua,et al.  Neural Synaptic Weighting With a Pulse-Based Memristor Circuit , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[24]  Wei Zhang,et al.  Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[25]  Ajay Joshi,et al.  Performance and energy models for memristor-based 1T1R RRAM cell , 2012, GLSVLSI '12.

[26]  Robinson E. Pino,et al.  Fast statistical model of TiO2 thin-film memristor and design implication , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[27]  S. Benderli,et al.  On SPICE macromodelling of TiO 2 memristors , 2009 .

[28]  Matthew D. Pickett,et al.  SPICE modeling of memristors , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[29]  Heng-Yuan Lee,et al.  A 5ns fast write multi-level non-volatile 1 K bits RRAM memory with advance write scheme , 2009, 2009 Symposium on VLSI Circuits.

[30]  Cong Xu,et al.  Impact of process variations on emerging memristor , 2010, Design Automation Conference.

[31]  Zhuangde Jiang,et al.  Characterization of line edge roughness and line width roughness of nano-scale typical structures , 2009, 2009 4th IEEE International Conference on Nano/Micro Engineered and Molecular Systems.

[32]  Vivek De,et al.  Design and reliability challenges in nanometer technologies , 2004, Proceedings. 41st Design Automation Conference, 2004..

[33]  György Cserey,et al.  Macromodeling of the Memristor in SPICE , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[34]  L. Chua.  Memristor-The missing circuit element , 1971 .

[35]  Yiran Chen,et al.  Geometry variations analysis of TiO2 thin-film and spintronic memristors , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[36]  G. Chen,et al.  A 0.13µm 8Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reduction , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[37]  Cong Xu,et al.  Design implications of memristor-based RRAM cross-point structures , 2011, 2011 Design, Automation & Test in Europe.

[38]  J. Yang,et al.  Switching dynamics in titanium dioxide memristive devices , 2009 .

[39]  Kinam Kim,et al.  A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O(5-x)/TaO(2-x) bilayer structures. , 2011, Nature materials.

[40]  D. Ielmini,et al.  Modeling the Universal Set/Reset Characteristics of Bipolar RRAM by Field- and Temperature-Driven Filament Growth , 2011, IEEE Transactions on Electron Devices.

[41]  Uri C. Weiser,et al.  TEAM: ThrEshold Adaptive Memristor Model , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[42]  D. Gilmer,et al.  Metal oxide resistive memory switching mechanism based on conductive filament properties , 2011 .

[43]  Klaus Witrisal,et al.  Memristor-based stored-reference receiver - the UWB solution? , 2009 .

[44]  Yiran Chen,et al.  Low-power dual-element memristor based memory design , 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

[45]  Peng Li,et al.  Dynamical Properties and Design Analysis for Nonvolatile Memristor Memories , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.