A fast carry propagation technique for parallel adders

A new technique is presented for the design of faster ripple-carry adders. Although this design is structurally inherited from the Manchester carry adder, it operates much faster and cuts down the propagation delay of the adder by close to 75 per cent. The main concept in this technique is the balance of charge throughout the nodes in the carry chain. This balance of charge, which is the consequence of selective pre-charging (SPC), causes the shifting of logic from 0 (or 1) to 1 (or 0) very quickly. The technique is implemented for a 4-bit adder module and the SPICE simulation results are compared with a similar Manchester carry adder.<<ETX>>