Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness

Increasing miniaturization is posing multiple challenges to electronic designers. In the context of multi-processor system-on-chips (MPSoCs), we focus on the problem of implementing efficient interconnect systems for devices which are ever more densely packed with parallel computing cores. Easily seen that traditional buses can not provide enough bandwidth, a revolutionary path to scalability is provided by packet-switched network-on-chips (NoCs), while a more conservative approach dictates the addition of bandwidth-rich components (e.g. crossbars) within the preexisting fabrics. While both alternatives have already been explored, a thorough contrastive analysis is still missing. In this paper, we bring crossbar and NoC designs to the chip layout level in order to highlight the respective strengths and weaknesses in terms of performance, area and power, keeping an eye on future scalability

[1]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[2]  Federico Angiolini,et al.  /spl times/pipes Lite: a synthesis oriented design library for networks on chips , 2005, Design, Automation and Test in Europe.

[3]  Altamiro Amadeu Susin,et al.  SoCIN: a parametric and scalable network-on-chip , 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

[4]  Drew Wingard.  MicroNetwork-based integration for SOCs , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[5]  Luca Benini,et al.  NoC synthesis flow for customized domain specific multiprocessor systems-on-chip , 2005, IEEE Transactions on Parallel and Distributed Systems.

[6]  Jörg Henkel,et al.  A methodology for design, modeling, and analysis of networks-on-chip , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[7]  Luca Benini,et al.  Fault Tolerance Overhead in Network-on-Chip Flow Control Schemes , 2005, 2005 18th Symposium on Integrated Circuits and Systems Design.

[8]  Sujit Dey,et al.  On-chip communication architecture for OC-768 network processors , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[9]  Ran Ginosar,et al.  QNoC: QoS architecture and design process for network on chip , 2004, J. Syst. Archit..

[10]  Alain Greiner,et al.  Micro-network for SoC: implementation of a 32-port SPIN network , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[11]  Jens Sparsø,et al.  Scheduling discipline for latency and bandwidth guarantees in asynchronous network-on-chip , 2005, 11th IEEE International Symposium on Asynchronous Circuits and Systems.

[12]  Dake Liu,et al.  SoCBUS: switched network on chip for hard real time embedded systems , 2003, Proceedings International Parallel and Distributed Processing Symposium.

[13]  Luca Benini,et al.  Networks on Chips: A Synthesis Perspective , 2005, PARCO.

[14]  Hoi-Jun Yoo,et al.  A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC platform , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[15]  Kees G. W. Goossens,et al.  Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip , 2003, DATE.

[16]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .