论文信息 - THEMIS Logic Simulator - A Mix Mode, Multi-Level, Hierarchical, Interactive Digital Circuit Simulator

THEMIS Logic Simulator - A Mix Mode, Multi-Level, Hierarchical, Interactive Digital Circuit Simulator

A new logic simulator called THEMIS (TM) Logic Simulator for the design of LSI, VLSI and PCBs is described. THEMIS supports design verification and test development from initial specification in behavioral and RTL languages to analysis of the final layout at the gate and switch level. To allow the simulation of an entire system or check the correctness of a single circuit, the different modeling techniques can be easily intermixed. THEMIS is a highly interactive simulator that minimizes a hardware engineer's time and effort to debug logic. This paper gives an overview of THEMIS and its use by design engineers.

Donald M. Schuler | Mahesh H. Doshi | Roderick B. Sullivan

[1] Ernst G. Ulrich,et al. Concurrent simulation of nearly identical digital networks , 1974, Computer.

[2] Roger Cleghorn. PRIMEAIDS: An Integrated Electrical Design Environment , 1981, 18th Design Automation Conference.

[3] Melvin A. Breuer,et al. Concurrent fault simulation and functional level modeling , 1977, DAC '77.

[4] Donald M. Schuler,et al. An efficient method of fault simulation for digital circuits modeled from boolean gates and memories , 1977, DAC '77.

[5] Melvin A. Breuer,et al. Digital System Simulation: Current Status and Future Trends or Darwin's Theory of Simulation , 1981, 18th Design Automation Conference.