Improvements of Instruction Scheduling

Instruction Scheduling as a compiler optimization is a very powerful technique to enable instruction level parallelism for many types of modern architectures. Instruction Scheduling can be used for making best fill of the micro-architecture pipeline (by minimizing the number of pipeline stalls) and is also of critical importance for keeping as busy as possible the multiple execution units for the architectures with parallel execution sets (like VLIW, EPIC or VLES architectures). This paper will present a set of improvements that can be brought to an instruction scheduling technique implemented in a real compiler for a VLIW architecture, where both pipeline aspects and multiple execution units are exploited. The improvements are based on practical and theoretical observations. They include a possible false-WAW dependence improvement, another improvement by considering inter-block latencies and also some improvements about hyper-block scheduling and IF-conversion integration with instruction scheduling.