A design of level interface for CMP based Cache system

This paper proposes a level interface for two-level Cache sub-system based on a 4-core CMP system. This interface module successfully connects L1-Cache and L2-Cache. Several optimizations are utilized in the design, which contribute to the realization of high-efficient communication between the two levels, lowering L1-Cache miss penalty, and the improvement of processing efficiency of access requests.

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