Signal integrity loss in SoC's interconnects: a diagnosis approach using embedded microprocessor

Presents a systematic approach for utilizing the microprocessor capabilities in testing the SoC's interconnects for signal integrity. We propose a graph representation of SoC/interconnects to minimize the test time while performing thorough test of interconnects for integrity loss. This is achieved by using the embedded microprocessor for two main tasks: (1) to dynamically determine the best test plan based on resource constraints and the test results from previous sessions, and (2) to execute the test plan, that includes test generation/delivery, signature analysis/diagnosis and process control.

[1]  Sujit Dey,et al.  Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores , 2002, J. Electron. Test..

[2]  Christos A. Papachristou,et al.  Microprocessor based testing for core-based system on chip , 1999, DAC '99.

[3]  Sujit Dey,et al.  Fault modeling and simulation for crosstalk in system-on-chip interconnects , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[4]  Lee Whetsel,et al.  An IEEE 1149.1 based test access architecture for ICs with embedded cores , 1997, Proceedings International Test Conference 1997.

[5]  Sujit Dey,et al.  Self-test methodology for at-speed test of crosstalk in chip interconnects , 2000, DAC.

[6]  J. L. Prince,et al.  Crosstalk analysis for high-speed pulse propagation in lossy electrical interconnections , 1993 .

[7]  Oh-Kyong Kwon,et al.  A new on-chip interconnect crosstalk model and experimental verification for CMOS VLSI circuit design , 2000 .

[8]  John Lillis,et al.  Interconnect Analysis and Synthesis , 1999 .

[9]  M. S. Harris.  Digital systems testing and testable design: M. Abramovici, M.A. Breur and A.D. Friedman. Computer Science Press, New York, 1991, 652 pp., £43.95 , 1992 .

[10]  Christos A. Papachristou,et al.  An ILP formulation to optimize test access mechanism in system-on-chip testing , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[11]  Mehrdad Nourani,et al.  Test pattern generation for signal integrity faults on long interconnects , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[12]  Rochit Rajsuman.  Testing a system-on-a-chip with embedded microprocessor , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[13]  Mehrdad Nourani,et al.  Built-in self-test for signal integrity , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[14]  Christos A. Papachristou,et al.  Improving bus test via IDDT and boundary scan , 2001, DAC '01.

[15]  Mehrdad Nourani,et al.  An IP packet forwarding technique based on partitioned lookup table , 2002, 2002 IEEE International Conference on Communications. Conference Proceedings. ICC 2002 (Cat. No.02CH37333).

[16]  Kenneth L. Shepard.  Design methodologies for noise in digital integrated circuits , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[17]  Brion L. Keller,et al.  Design and implementation of a parallel weighted random pattern and logic built in self test algorithm , 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

[18]  Sujit Dey,et al.  High-level crosstalk defect simulation for system-on-chip interconnects , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[19]  Mehrdad Nourani,et al.  Testing interconnects for noise and skew in gigahertz SoCs , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[20]  Melvin A. Breuer,et al.  Test generation in VLSI circuits for crosstalk noise , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[21]  Robert G. Meyer,et al.  Analysis and Design of Analog Integrated Circuits , 1993 .

[22]  Nur A. Touba,et al.  Testing embedded cores using partial isolation rings , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[23]  Jacob A. Abraham,et al.  Automatic test pattern generation for crosstalk glitches in digital circuits , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[24]  Hans-Joachim Wunderlich,et al.  Accumulator based deterministic BIST , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).