Leakage current reduction using modified gate replacement technique for CMOS VLSI circuit

In recent years, leakage power dominates the dynamic power in nanoscale CMOS VLSI circuits. This research paper describes different leakage mechanisms that includes subthreshold and gate leakage current. A novel approach of reduction in leakage current is proposed which is primarily based on the conventional gate replacement technique. This approach is more effective in circuits with higher logic depth. A comparative analysis is performed between the conventional and modified gate replacement mechanisms. Using the modified technique, the overall leakage current and number of replacements are reduced by 13.5% and 33.5% respectively as compared to the conventional one.

[1]  Massoud Pedram,et al.  Leakage current reduction in CMOS VLSI circuits by input vector control , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Saibal Mukhopadhyay,et al.  Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.

[3]  Sunil P. Khatri,et al.  A Simultaneous Input Vector Control and Circuit Modification Technique to Reduce Leakage with Zero Delay Penalty , 2010, TODE.

[4]  K. Roy,et al.  Accurate modeling of transistor stacks to effectively reduce total standby leakage in nano-scale CMOS circuits , 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

[5]  Farid N. Najm,et al.  A gate-level leakage power reduction method for ultra-low-power CMOS circuits , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

[6]  Farid N. Najm,et al.  Design techniques for gate-leakage reduction in CMOS circuits , 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

[7]  John P. Hayes,et al.  Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction , 2006, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Gang Qu,et al.  A combined gate replacement and input vector control approach for leakage current reduction , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Narayanan Vijaykrishnan,et al.  Accurate stacking effect macro-modeling of leakage power in sub-100 nm circuits , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[10]  C. P. Ravikumar,et al.  Leakage power estimation for deep submicron circuits in an ASIC design environment , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[11]  Mark C. Johnson,et al.  Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks , 1998, ISLPED '98.