Chip design of memory-architecture-based minimum-classification-error

This paper proposes the chip design of memory-architecture-based minimum-classification-error (MCE). The major contribution is of this MCE chip is to increase the discriminative capability rather than to fit the distribution of data in the application of classification problems. It includes matrix-function, exponent, logarithm, sigmoid function, and square-root. To implement MCE, UMC 90nm standard cell-library is adopted. The chip area is 8.07mm2, and the power consumption is 3.6393mW. The maximum operating frequency is 83MHz.

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