Selection of Well Contact Densities for Latchup-Immune Minimal-Area ICs

Heavy ion data for custom SRAMs fabricated in a 45-nm CMOS technology demonstrate the effects of N- and P-well contact densities on single-event latchup. Although scaling has improved latchup robustness, process-level immunity has not been achieved, indicating a continued need for latchup mitigation techniques. A simple, algorithmic approach for selecting N- and P-well contact densities is described that ensures latchup immunity while minimizing the area penalty.

[1]  G. L. Hash,et al.  Impact of Heavy Ion Energy and Nuclear Interactions on Single-Event Upset and Latchup in Integrated Circuits , 2007, IEEE Transactions on Nuclear Science.

[2]  A.F. Witulski,et al.  Analysis of Parasitic PNP Bipolar Transistor Mitigation Using Well Contacts in 130 nm and 90 nm CMOS Technology , 2007, IEEE Transactions on Nuclear Science.

[3]  D. G. Mavis,et al.  Employing radiation hardness by design techniques with commercial integrated circuit processes , 1997, 16th DASC. AIAA/IEEE Digital Avionics Systems Conference. Reflections to the Future. Proceedings.

[4]  Ronald R. Troutman.  Latchup in CMOS Technology , 1986 .

[5]  D. Schroder.  Semiconductor Material and Device Characterization , 1990 .

[6]  peixiong zhao,et al.  Implications of Nuclear Reactions for Single Event Effects Test Methods and Analysis , 2006, IEEE Transactions on Nuclear Science.

[7]  J.M. Hutson,et al.  The Effects of Scaling and Well and Substrate Contact Placement on Single Event Latchup in Bulk CMOS Technology , 2005, 2005 8th European Conference on Radiation and Its Effects on Components and Systems.

[8]  G. L. Hash,et al.  Effects of particle energy on proton-induced single-event latchup , 2005, IEEE Transactions on Nuclear Science.

[9]  Allan H. Johnston,et al.  The influence of VLSI technology evolution on radiation-induced latchup in space systems , 1996 .

[10]  L.W. Massengill,et al.  Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design , 2005, IEEE Transactions on Nuclear Science.

[11]  C. Duvvury,et al.  Latch-up in 65nm CMOS technology: a scaling perspective , 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

[12]  Ronald R. Troutman,et al.  Latchup in CMOS Technology: The Problem and Its Cure , 1986 .

[13]  peixiong zhao,et al.  Evidence for Lateral Angle Effect on Single-Event Latchup in 65 nm SRAMs , 2009, IEEE Transactions on Nuclear Science.

[14]  H.H.K. Tang,et al.  Measurement of the flux and energy spectrum of cosmic-ray induced neutrons on the ground , 2004, IEEE Transactions on Nuclear Science.

[15]  E. Blackmore,et al.  LET spectra of proton energy levels from 50 to 500 MeV and their effectiveness for single event effects characterization of microelectronics , 2003 .

[16]  J.M. Hutson,et al.  The Effects of Angle of Incidence and Temperature on Latchup in 65 nm Technology , 2007, IEEE Transactions on Nuclear Science.