Novel circuit technique for reduction of active drain current in series/parallel PMOS transistors stack
暂无分享,去创建一个
[1] Stephan Henzler. Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies (Springer Series in Advanced Microelectronics) , 2006 .
[2] J. Figueras,et al. Characterization of leakage power in CMOS technologies , 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).
[3] B. M. Gordon,et al. Supply and threshold voltage scaling for low power CMOS , 1997, IEEE J. Solid State Circuits.
[4] Anantha P. Chandrakasan,et al. Low-power CMOS digital design , 1992 .
[5] Kaushik Roy,et al. Low-Power CMOS VLSI Circuit Design , 2000 .
[6] Ralph Etienne-Cummings,et al. Power dissipation sources and possible control techniques in ultra deep submicron CMOS technologies , 2006, Microelectron. J..