Why hybridize NEMS with CMOS?
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[1] Elad Alon,et al. Demonstration of Integrated Micro-Electro-Mechanical Relay Circuits for VLSI Applications , 2011, IEEE Journal of Solid-State Circuits.
[2] Vladimir Stojanovic,et al. Demonstration of integrated micro-electro-mechanical switch circuits for VLSI applications , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).
[3] T. Liu,et al. Pull-In and Release Voltage Design for Nanoelectromechanical Field-Effect Transistors , 2009, IEEE Transactions on Electron Devices.
[4] Vladimir Stojanovic,et al. Integrated circuit design with NEM relays , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.
[5] Elad Alon,et al. Four-Terminal-Relay Body-Biasing Schemes for Complementary Logic Circuits , 2010, IEEE Electron Device Letters.
[6] Poras T. Balsara,et al. NEM Relay-Based Sequential Logic Circuits for Low-Power Design , 2013, IEEE Transactions on Nanotechnology.
[7] K. Kuhn,et al. Scaling Limits of Electrostatic Nanorelays , 2013, IEEE Transactions on Electron Devices.
[8] S. Seshu. Review: Edward F. Moore, Table of Four-Relay Contact Networks , 1959 .
[9] Daniel Grogg,et al. Fundamental scaling properties of electro-mechanical switches , 2012 .
[10] Jun‐Bo Yoon,et al. A sub-1-volt nanoelectromechanical switching device. , 2013, Nature nanotechnology.
[11] Claude E. Shannon,et al. A symbolic analysis of relay and switching circuits , 1938, Transactions of the American Institute of Electrical Engineers.
[12] R. Brayton. Factoring logic functions , 1987 .
[13] Edward F. Moore,et al. Logical design of electrical circuits , 1959 .
[14] Mingzhe Jiang. BDD Based Logic Synthesis of MEM Relay Circuits , 2013 .
[15] Themistoklis Haniotakis,et al. A Methodology for Transistor-Efficient Supergate Design , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[16] Elad Alon,et al. Mechanical Computing Redux: Relays for Integrated Circuit Applications , 2010, Proceedings of the IEEE.
[17] Vladimir Stojanovic,et al. Relays do not leak - CMOS does , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).
[18] Tsu-Jae King Liu,et al. 4-terminal relay technology for complementary logic , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).
[19] Owen Y Loh,et al. Nanoelectromechanical contact switches. , 2012, Nature nanotechnology.
[20] Gianluca Piazza,et al. 1 Volt digital logic circuits realized by stress-resilient ALN parallel dual-beam MEMS relays , 2012, 2012 IEEE 25th International Conference on Micro Electro Mechanical Systems (MEMS).
[21] Arunita Jaekel,et al. A multilevel factorization technique for pass transistor logic , 1996, Proceedings of 9th International Conference on VLSI Design.
[22] Massimo Alioto,et al. Enhancing the Static Noise Margins by Upsizing Length for Ultra-Low Voltage/Power/Energy Gates , 2014, J. Low Power Electron..
[23] S. Dutta. Floating-point Unit ( FPU ) Designs with Nano-electromechanical ( NEM ) Relays , 2013 .
[24] Tsu-Jae King Liu,et al. Microelectromechanical Relay and Logic Circuit Design for Zero Crowbar Current , 2014, IEEE Transactions on Electron Devices.
[25] Sachin S. Sapatnekar,et al. BDD decomposition for delay oriented pass transistor logic synthesis , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[26] D. Markovic,et al. The relay reborn , 2012, IEEE Spectrum.
[27] Tsu-Jae King Liu,et al. Design, Optimization, and Scaling of MEM Relays for Ultra-Low-Power Digital Logic , 2011, IEEE Transactions on Electron Devices.
[28] A. I. Reis,et al. Transistor-level optimization of CMOS complex gates , 2013, 2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS).