Optimizing the control-unit through the resynchronization of operations

Most approaches to control-unit optimization use a finite state machine model, where operations are bound to control states. However, when synthesizing circuits from a higher, more abstract level of hardware specification that supports concurrency and synchronization, these approaches may be overly restrictive. We present a strategy for optimizing control circuits based on resynchronization of operations such that the original specification under timing constraints is still satisfied but with a lower control implementation cost. We use a general constraint graph model to capture the high level specification; the model supports unbounded delay operations, detailed timing constraints, and concurrency. We introduce the notion of synchronization redundancy and formulate the optimization problem as the task of mapping operations to synchronization points. We present algorithms to find a minimal control cost implementation. Results of applying the technique within the framework of the Hercules/Hebe High-level Synthesis system are presented.