Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions

Due to the intrinsic masking effects of combinational circuits in digital designs, Single-Event Transient (SET) effects were considered irrelevant compared to the data rupture caused by Single-Event Upset (SEU) effects. However, the importance of considering SET in Very-Large-System-Integration (VLSI) circuits increases given the reduction of the transistor dimensions and the logic data path depth in advanced technology nodes. Accordingly, the threat of SET in electronics systems for space applications must be carefully addressed along with the SEU characterization. In this work, a systematic prediction methodology to assess and improve the SET immunity of digital circuits is presented. Further, the applicability to full-custom and cell-based design methodologies are discussed, and an analysis based on signal probability and pin assignment is proposed to achieve a more application-efficient SET-aware optimization of synthesized circuits. For instance, a SET-aware pin assignment can provide a reduction of 37% and 16% on the SET rate of a NOR gate for a Geostationary Orbit (GEO) and the International Space Station (ISS) orbit, respectively.

[1]  Philippe Roche,et al.  Factors that impact the critical charge of memory elements , 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

[2]  Guilherme Flach,et al.  Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  R.W. Brodersen,et al.  A dynamic voltage scaled microprocessor system , 2000, IEEE Journal of Solid-State Circuits.

[4]  Farid N. Najm.  Improved estimation of the switching activity for reliability prediction in VLSI circuits , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[5]  Kewal K. Saluja,et al.  Soft error reduction through gate input dependent weighted sizing in combinational circuits , 2011, 2011 12th International Symposium on Quality Electronic Design.

[6]  A. Taber,et al.  Single event upset in avionics , 1993 .

[7]  S. Wender,et al.  Single event phenomena in atmospheric neutron environments , 1993 .

[8]  peixiong zhao,et al.  Scaling Trends in SET Pulse Widths in Sub-100 nm Bulk CMOS Processes , 2010, IEEE Transactions on Nuclear Science.

[9]  L. W. Massengill,et al.  Single Event Transients in Digital CMOS—A Review , 2013, IEEE Transactions on Nuclear Science.

[10]  Tsutomu Sasao,et al.  Logic Synthesis and Verification , 2013 .

[11]  Christopher Frost,et al.  Voltage scaling and aging effects on soft error rate in SRAM-based FPGAs , 2014, Microelectron. Reliab..

[12]  J.-L. Autran,et al.  Analysis of the charge sharing effect in the SET sensitivity of bulk 45 nm standard cell layouts under heavy ions , 2018, Microelectron. Reliab..

[13]  Frederic Wrobel,et al.  Detailed history of recoiling ions induced by nucleons , 2008, Comput. Phys. Commun..

[14]  Shuming Chen,et al.  A Constrained Layout Placement Approach to Enhance Pulse Quenching Effect in Large Combinational Circuits , 2014, IEEE Transactions on Device and Materials Reliability.

[15]  P.H. Eaton,et al.  Digital Single Event Transient Trends With Technology Node Scaling , 2006, IEEE Transactions on Nuclear Science.

[16]  Paul D. Franzon,et al.  FreePDK: An Open-Source Variation-Aware Design Kit , 2007, 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07).

[17]  B. L. Bhuva,et al.  Analysis of soft error rates in combinational and sequential logic and implications of hardening for advanced technologies , 2010, 2010 IEEE International Reliability Physics Symposium.

[18]  R. Baumann.  The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction , 2002, Digest. International Electron Devices Meeting,.

[19]  L. Artola,et al.  Implications of Work-Function Fluctuation on Radiation Robustness of FinFET XOR Circuits , 2017, 2017 17th European Conference on Radiation and Its Effects on Components and Systems (RADECS).

[20]  Bing J. Sheu,et al.  BSIM: Berkeley short-channel IGFET model for MOS transistors , 1987 .

[21]  G. Hubert,et al.  Operational SER Calculations on the SAC-C Orbit Using the Multi-Scales Single Event Phenomena Predictive Platform (MUSCA ${\rm SEP}^{3}$) , 2009, IEEE Transactions on Nuclear Science.

[22]  Robert G. Meyer,et al.  An engineering model for short-channel MOS devices , 1988 .

[23]  F. Wrobel,et al.  Anthology of the Development of Radiation Transport Tools as Applied to Single Event Effects , 2013, IEEE Transactions on Nuclear Science.

[24]  Brandon Reddell,et al.  Calculating Spacecraft Single Event Environments with FLUKA: Investigating the Effects of Spacecraft Material Atomic Number on Secondary Particle Showers, Nuclear Reactions, and Linear Energy Transfer (LET) Spectra, Internal to Spacecraft Avionics Materials, at High Shielding Mass , 2010, 2011 IEEE Radiation Effects Data Workshop.

[25]  F. Saigné,et al.  Radiation hardening efficiency of gate sizing and transistor stacking based on standard cells , 2019, Microelectronics Reliability.

[26]  Fernanda Gusmão de Lima Kastensmidt,et al.  Evaluation of radiation-induced soft error in majority voters designed in 7 nm FinFET technology , 2017, Microelectron. Reliab..

[27]  D. Munteanu,et al.  Modeling and Simulation of Single-Event Effects in Digital Devices and ICs , 2008, IEEE Transactions on Nuclear Science.

[28]  J. Ziegler,et al.  SRIM – The stopping and range of ions in matter (2010) , 2010 .

[29]  F. Wrobel,et al.  Impact of Complex Logic Cell Layout on the Single-Event Transient Sensitivity , 2019, IEEE Transactions on Nuclear Science.

[30]  Jonathan Rose,et al.  Measuring the Gap Between FPGAs and ASICs , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[31]  Kartik Mohanram,et al.  Gate sizing to radiation harden combinational logic , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[32]  Denis Teixeira Franco,et al.  Reliability analysis of logic circuits based on signal probability , 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

[33]  Lloyd W. Massengill,et al.  Effects of Threshold Voltage Variations on Single-Event Upset Response of Sequential Circuits at Advanced Technology Nodes , 2017, IEEE Transactions on Nuclear Science.

[34]  J. S. Kauppila,et al.  Effect of Transistor Variants on Single-Event Transients at the 14-/16-nm Bulk FinFET Technology Generation , 2018, IEEE Transactions on Nuclear Science.

[35]  Paulo F. Butzen,et al.  Probabilistic Method for Reliability Estimation of SP- Networks considering Single Event Transient Faults , 2018, 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

[36]  B. L. Bhuva,et al.  Reliability-Aware Synthesis of Combinational Logic With Minimal Performance Penalty , 2013, IEEE Transactions on Nuclear Science.

[37]  Luis Entrena,et al.  Constrained Placement Methodology for Reducing SER Under Single-Event-Induced Charge Sharing Effects , 2012, IEEE Transactions on Nuclear Science.

[38]  A.P. Chandrakasan,et al.  Dual-threshold voltage techniques for low-power digital circuits , 2000, IEEE Journal of Solid-State Circuits.

[39]  F. Wrobel,et al.  Criterion for SEU occurrence in SRAM deduced from circuit and device Simulations in case of neutron-induced SER , 2005, IEEE Transactions on Nuclear Science.

[40]  Frédéric Saigné,et al.  MC-ORACLE: A tool for predicting Soft Error Rate , 2011, Comput. Phys. Commun..

[41]  M. Gaillardin,et al.  Modeling Single Event Transients in Advanced Devices and ICs , 2015, IEEE Transactions on Nuclear Science.

[42]  Paul S. Zuchowski,et al.  A hybrid ASIC and FPGA architecture , 2002, ICCAD 2002.

[43]  Gilson I. Wirth,et al.  Design Flow Methodology for Radiation Hardened by Design CMOS Enclosed-Layout-Transistor-Based Standard-Cell Library , 2018, J. Electron. Test..

[44]  Cristina Meinhardt,et al.  Evaluation of heavy-ion impact in bulk and FDSOI devices under ZTC condition , 2017, Microelectron. Reliab..

[45]  Behnam Ghavami,et al.  Soft Error Reliability Improvement of Digital Circuits by Exploiting a Fast Gate Sizing Scheme , 2019, IEEE Access.

[46]  R.A. Reed,et al.  Integrating Circuit Level Simulation and Monte-Carlo Radiation Transport Code for Single Event Upset Analysis in SEU Hardened Circuitry , 2008, IEEE Transactions on Nuclear Science.