Adding Fast Interrupts to Superscalar Processors

The hardware cost of taking an interrupt is increasing as processors become more superscalar. Using FLIP, an aggressively superscalar processor which we have designed and tested in Verilog, we demonstrate that interrupts can be fast and inexpensive. We trace individual signals through FLIP’s pipeline stages to show that fast interrupts require negligible new hardware. Except for linkage information, interrupts reuse existing branch mechanisms. An asynchronous interrupt acts as an immediate jump instruction, while a synchronous interrupt acts as a mispredicted branch. Although we concentrate on user-level interrupts, we show that kernel-level interrupts can be handled identically with the addition of protection mode bits to identify the protection mode of every outstanding instruction. In blending fast interrupts into the superscalar processor, we address two new problems. The first problem arises from fast synchronous interrupts. Because most instructions can cause an interrupt, the processor must be able to revert to its state prior to most instructions, not just mispredicted branches. This ubiquitousness of reversion leads us to design a new renaming data structure. Our renaming data structure can revert to the state prior to any outstanding instruction by updating a single pointer. The entire structure consists of the outstanding renaming bindings plus a simple scan circuit to look up the latest binding. The second problem arises from the interaction of mispredicted branches and asynchronous interrupts. An asynchronous interrupt can sometimes vanish if a branch which dynamically precedes the interrupt handler mispredicts. We offer a simple solution in which the processor remembers an outstanding interrupt and replays the interrupt in case of a preceding misprediction.