A high purity, high speed direct digital synthesizer

A Direct Digital Synthesizer (DDS), that clocks at 500 MHz, has been constructed in a 70 pin hybrid circuit package that is 1.14/spl times/2.33/spl times/0.2 inches. Spectral purity is better than -55 dBc worst case spur, up to 245 MHz output frequency. TTL compatible, parallel lines are provided for 28 bits of frequency and 8 bits of phase control. The hybrid is based on two GaAs chips, a HBT digital to analog converter and a MESFET accumulator/ROM combination. Two silicon ECL chips are used for clock amplification and distribution. This allows an AC coupled sinusoidal input clock of 0 dBm nominal amplitude. Power dissipation is typically 5 watts using +5.0, -5.2, and -2.2 volt supplies. This paper describes the DDS architecture, design of the GaAs chips, and special problems encountered during development of the hybrid.