An optimum VLSI design of a 16-BIT ALU

The key parameters for the performance measure of any VLSI design are logic delay, power consumption and chip area. This paper describes the VLSI design of a 16 Bit ALU and design is optimized in terms of Speed, Power Consumption and Chip Area. Different logic families are used in the design for various logic modules. The choice of logic families for each module is determined by considering speed and power consumption as the important parameters offered by each logic family. The adder circuit being the most important module used by the arithmetic operations of an ALU, detailed analysis of the variety of adder circuit configurations are carried out and the best suited configuration for the ALU design i.e. Carry Skip Adder configuration is used to design the optimum ALU. Finally a 16 bit Arithmetic Logic unit is designed using mixed logic families such as CMOS for basic logic functions, pseudo-NMOS for AND logic and Pass Transistor logic for multiplexers, in order to optimize the overall performance of the design. Schematic editor DSCH is used to validate the design at gate level implementation and IC Layout editor Microwind is used to implement the chip level design.