The importance of including thermal effects in estimating the effectiveness of power reduction techniques

It is shown in this paper that thermal effects have to be an integral part of estimating the effectiveness of power reduction techniques in nanometer scale technologies, and its inclusion always results in higher reduction in power than conventional estimations. Four different power reduction techniques for on-chip buses are used as examples to show the necessity of including thermal effects. Simulation results in a 70nm technology show that thermal-aware estimations of power savings are 17-38% higher than conventional estimations that do not include thermal effects

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