A Dynamically Reconfigurable Processor with Multi-Mode Operation Based on Newly Developed Full-Adder/D-Flip-Flop Merged Module (FDMM)

l.Introduction Dynamically customizable and reconfigurable hardware architecture for a specific task on demand is one of the most important issues to bring out a novel-computing paradigm in the era of system LSI. This is because it can fill a wide gap between hardware performance and software programmability []. The gap has been shown, for instance, as a difference between application-specific LSI (ASIC) with intensive performance and field programmable gate anay (IPGA) with intensive programmability. Moreover, in conventional FPCA, customizable modules are composed of large combinational logic part and optional flip-flop part to perform any functions by utilizing its vast programmability. Therefore, developing an original type of customizable module that has both ASIC's and FPGAs merit, which eliminates redundant programmability preserving necessary specific functionalities for performance, is most promising in order to realize dynamically reconfigurable processor. This is our focus. We have developed an original full-adder / D-flip-flop merged module ([DMM) and fabricated a chip including a 4 x 4 wray of FDMMs with 0.6pm CMOS technologyT. Utiliring the chip and circuitry concept, near to the future, we are planning to apply these to some signal processing applications such as encrypting, image filtering, multi-task digital signal processing, and customizable-coding of microprocessor, memory, and other standard products. In this paper, we propose the developed FDMM and introduce the fabricated system architecture of dynamically reconfigurable multi-mode processor based on FDMM in detail.