Invisible delay quality - SDQM model lights up what could not be seen

The quality of delay testing focused on small delay defects is not clear when traditional fault models are used. We therefore evaluated the feasibility of using the statistical delay quality model (SDQM) - which reflects fabrication process quality, design delay quality, test timing accuracy, and test pattern quality - by using a commercial automatic test program generation (ATPG) tool to apply it to a large data set. The SDQM can also provide a measure predicting the defect level of a chip, and by simulating test patterns we show experimentally here that this measure can be calculated within a reasonable CPU time when using a reasonable amount of memory. Because we found when using SDF information to calculate path lengths accurately that the transition test patterns are not good at detecting small delay defects in long paths, a new test algorithm that detects small delay defects should be developed

[1]  Irith Pomeranz,et al.  On n-detection test sets and variable n-detection test sets for transition faults , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[2]  Nandakumar Nityananda Tendolkar.  Analysis of Timing Failures Due to Random AC Defects in VLSI Modules , 1985, DAC 1985.

[3]  Phil Nigh,et al.  Test method evaluation experiments and data , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[4]  L. Wang,et al.  Experience in critical path selection for deep sub-micron delay test and timing validation , 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

[5]  Charles E. Radke,et al.  Delay test effectiveness evaluation of LSSD-Based VLSI logic circuits , 1991, 28th ACM/IEEE Design Automation Conference.

[6]  Ananta K. Majhi,et al.  On hazard-free patterns for fine-delay fault testing , 2004 .

[7]  M. Ray Mercer,et al.  Delay Testing Quality in Timing-Optimized Designs , 1991, 1991, Proceedings. International Test Conference.

[8]  Y. Sato,et al.  Evaluation of the statistical delay quality model , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[9]  Edward J. McCluskey,et al.  Delay defect screening using process monitor structures , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[10]  M. Ray Mercer,et al.  Using logic models to predict the detection behavior of statistical timing defects , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[11]  Phil Nigh,et al.  Test Method Evaluation Experiments & Data , 2000 .

[12]  D. S. Cleverley,et al.  Product quality level monitoring and control for logic chips and modules , 1983 .

[13]  M. Ray Mercer,et al.  Statistical delay fault coverage and defect level for delay faults , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.