High-Efficient Circuits for Ternary Addition
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[1] Resit Sendag,et al. Multiple-valued logic buses for reducing bus energy in low-power systems , 2006 .
[2] Keivan Navi,et al. Design and analysis of a high-performance CNFET-based Full Adder , 2012 .
[3] S. Hirsch. Carbon Nanotubes Synthesis Structure Properties And Applications , 2016 .
[4] Mohd. Hasan,et al. Carbon nanotube field effect transistors for high performance analog applications: An optimum design approach , 2010, Microelectron. J..
[5] T. Nakamura,et al. Realization of quaternary logic circuits by n-channel MOS devices , 1986 .
[6] Jörg Appenzeller,et al. Carbon Nanotubes for High-Performance Electronics—Progress and Prospect , 2008, Proceedings of the IEEE.
[7] Arash Ahmadi,et al. Effect of variability in SWCNT-based logic gates , 2009, Proceedings of the 2009 12th International Symposium on Integrated Circuits.
[8] K. Maharatna,et al. Modeling SWCNT Bandgap and Effective Mass Variation Using a Monte Carlo Approach , 2010, IEEE Transactions on Nanotechnology.
[9] C. Dekker,et al. Logic Circuits with Carbon Nanotube Transistors , 2001, Science.
[10] Elena Dubrova,et al. Multiple-Valued Logic in VLSI: Challenges and Opportunities , 1999 .
[11] H. Inokawa,et al. A multiple-valued logic with merged single-electron and MOS transistors , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
[12] F. Lombardi,et al. A novel CNTFET-based ternary logic gate design , 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.
[13] Yong-Bin Kim,et al. High speed and low power transceiver design with CNFET and CNT bundle interconnect , 2010, 23rd IEEE International SOC Conference.
[14] V. T. Ingole,et al. Design And Implementation Of 2 Bit Ternary ALU Slice , 2005 .
[15] H.-S. Philip Wong,et al. Carbon nanotube computer , 2013, Nature.
[16] P. Avouris,et al. Carbon Nanotube Inter- and Intramolecular Logic Gates , 2001 .
[17] Peiman Keshavarzian,et al. A Novel CNTFET-based Ternary Full Adder , 2014, Circuits Syst. Signal Process..
[18] F. Remacle,et al. Balanced ternary addition using a gated silicon nanowire , 2011 .
[19] MahyarShahsavari. Low Power CNTFET-Based Ternary Full Adder Cell for Nanoelectronics , 2012 .
[20] Keivan Navi,et al. Design of energy-efficient and robust ternary circuits for nanotechnology , 2011, IET Circuits Devices Syst..
[21] Stanley L. Hurst,et al. Multiple-Valued Logic—its Status and its Future , 1984, IEEE Transactions on Computers.
[22] Yong-Bin Kim,et al. CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits , 2011, IEEE Transactions on Nanotechnology.
[23] Yong-Bin Kim,et al. Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability , 2010, Integr..
[24] Ken Mai,et al. The future of wires , 2001, Proc. IEEE.
[25] Keivan Navi,et al. A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits , 2013, IET Comput. Digit. Tech..
[26] Yong-bin Kim,et al. Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor , 2011 .
[27] Mark S. Lundstrom,et al. Theory of ballistic nanotransistors , 2003 .
[28] K. Roy,et al. Carbon-nanotube-based voltage-mode multiple-valued logic design , 2005, IEEE Transactions on Nanotechnology.
[29] Jorge A. Navas,et al. Negative Ternary Set-Sharing , 2008, ICLP.
[30] Antonio Rubio,et al. Manufacturing variability analysis in Carbon Nanotube Technology: A comparison with bulk CMOS in 6T SRAM scenario , 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.