论文信息 - FPGA implementation of real-time image convolutions with three level of memory hierarchy

FPGA implementation of real-time image convolutions with three level of memory hierarchy

In this paper, a customized image convolution processor with three level memory hierarchy is implemented on Xilinx VirtexE FPGAs. Due to its fully pipelined datapath for calculations and streamlined data flow architecture, the processor has the performance close to that of TI highest performance C64x processor at less than 1/8 of the clock frequency with substantial I/O bandwidth reductions. Furthermore, potential power savings are envisioned in future ASIC implementations by meaningful memory hierarchy explorations. In addition, a dedicated controller composed of Finite State Machine with incremental branch optimization architecture is developed to control all the operations in calculations and data transfer.

Viktor Öwall | Hongtu Jiang

[1] Viktor Öwall,et al. A Custom Image Convolution DSP with a Sustained Calculation Capacity of >1 GMAC/s and Low I/O Bandwidth , 1999, J. VLSI Signal Process..

[2] Francky Catthoor,et al. Custom Memory Management Methodology , 1998, Springer US.

[3] Ernest Jamro,et al. FPGA implementation of addition as a part of the convolution , 2001, Proceedings Euromicro Symposium on Digital Systems Design.

[4] Viktor Öwall. Synthesis of Controllers from a Range of Controller Architectures , 1994 .

[5] R.W.M. Smith,et al. Comparison of a programmable DSP and a FPGA for real-time multiscale convolution , 1998 .