An Efficient Test for a Transistion Signalling based Up-/Down-Counter

This paper reports on a formal model for testing transition signalling logic in presence of (multiple) stuck-at faults and how this model can be applied to an Up-/Down-Counter Module. The Counter forms a key element in the fault-tolerant distributed clock generation circuit developed in the course of our DARTS (Distributed Algorithms for Robust Tick Synchronization) project, but is sufficiently general to be of interest for other transition signalling circuits, too. We point out the particular problems of testing a self-timed logic module and devise a very efficient test with 100% coverage for our Counter Module.

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