A −104dBc/Hz in-band phase noise 3GHz all digital PLL with phase interpolation based hierarchical time to digital convertor

An ADPLL which uses a time-to-digital convertor with <0.13rad resolution achieves LO generation at 3GHz with −104dBc/Hz in-band phase noise. The fine and stable resolution is derived by known phase interpolation circuits. It is fabricated in a 65nm CMOS process and the active area is 0.18mm2. keywords: ADPLL, TDC, phase interpolator.

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