论文信息 - Low-power video decoding system using a reconfigurable processor

Low-power video decoding system using a reconfigurable processor

A reconfigurable processor based video decoding system with bistream decoding instruction and memory processing co-processor is presented. Experimental results show that the performance is enhanced about 42% than processor only system. We also estimate that the power consumption is lower than the hardware system about 24% at SD resolution.

Do-Hyung Kim | Shihwa Lee | Doo Hyun Kim | Wonchang Lee | Joon Ho Song

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