A Non-Blocking Multithreaded Architecture

In this paper we present a new approach to building multithreaded uni-processors. Our innovativeness stems from an architecture with non-blocking threads where all memory accesses are decoupled from the thread execution. Data is pre-loaded into the thread context (registers), and all results are "post-stored" after the completion of the thread execution. The decoupling of memory accesses from thread execution requires a separate unit to perform the necessary pre-loads and post-stores, and controlling the allocation of hardware thread contexts to enabled threads. This separation facilitates for achieving high locality and minimizing the impact of distribution and hierarchy in large memory systems. We present our preliminary results obtained from a Monte Carlo simulator that compares the performance of the proposed system with conventional architectures for randomly generated threads.