Optimizing deterministic garbage collection in NAND flash storage systems

NAND flash has been widely adopted as storage devices in real-time embedded systems. However, garbage collection is needed to reclaim space and introduces a lot of time overhead. As the worst system latency is determined by the worst-case execution time of garbage collection in NAND flash, it is important to optimize garbage collection so as to give a deterministic worst system latency. On the other hand, since the garbage collection does not happen very often, optimizing garbage collection should not bring too much overhead to the average system latency. This paper presents for the first time a worst-case and average-case joint optimization scheme for garbage collection in NAND flash. With our scheme, garbage collection can be postponed to the latest stage so improves the average system latency. By combining partial garbage collection and over-provisioning, our scheme can guarantee that one free block is enough to hold all pages from both write requests and valid-page copies. The experiments have been conducted on a real embedded platform and the results show that our technique can improve both worstcase and average-case system latency compared with the previous works.

[1]  Wei-Che Tseng,et al.  Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Zili Shao,et al.  Write-activity-aware page table management for PCM-based embedded systems , 2012, 17th Asia and South Pacific Design Automation Conference.

[3]  Yiran Chen,et al.  Processor caches built using multi-level spin-transfer torque RAM cells , 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

[4]  Liang Shi,et al.  Cooperating Write Buffer Cache and Virtual Memory Management for Flash Memory Based Systems , 2011, 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium.

[5]  Yiran Chen,et al.  STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design view , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[6]  Sang-Won Lee,et al.  A log buffer-based flash translation layer using fully-associative sector translation , 2007, TECS.

[7]  Youngjae Kim,et al.  DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings , 2009, ASPLOS.

[8]  Jongman Kim,et al.  Preemptible I/O Scheduling of Garbage Collection for Solid State Drives , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Zili Shao,et al.  A Two-Level Caching Mechanism for Demand-Based Page-Level Address Mapping in NAND Flash Memory Storage Systems , 2011, 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium.

[10]  Yu Wang,et al.  ICE: Inline calibration for memristor crossbar-based computing engine , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[11]  Tony Givargis,et al.  Deterministic service guarantees for nand flash using partial block cleaning , 2008, CODES+ISSS '08.

[12]  Jacques-Olivier Klein,et al.  Magnetic Adder Based on Racetrack Memory , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  Wei-Che Tseng,et al.  Write activity reduction on non-volatile main memories for embedded chip multiprocessors , 2013, TECS.

[14]  Tei-Wei Kuo,et al.  Real-time garbage collection for flash-memory storage systems of real-time embedded systems , 2004, TECS.

[15]  Laurence T. Yang,et al.  A Real-Time Flash Translation Layer for NAND Flash Memory Storage Systems , 2012, IEEE Transactions on Multi-Scale Computing Systems.

[16]  Zili Shao,et al.  MNFTL: An efficient flash translation layer for MLC NAND flash memory storage systems , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[17]  Jacques-Olivier Klein,et al.  Cross-Point Architecture for Spin-Transfer Torque Magnetic Random Access Memory , 2012, IEEE Transactions on Nanotechnology.

[18]  Jeffrey Katcher,et al.  PostMark: A New File System Benchmark , 1997 .

[19]  Zili Shao,et al.  A Space Reuse Strategy for Flash Translation Layers in SLC NAND Flash Memory Storage Systems , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[20]  Zili Shao,et al.  Demand-based block-level address mapping in large-scale NAND flash storage systems , 2010, 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[21]  阿米尔·班 Flash File System , 1994 .

[22]  KuoTei-Wei,et al.  An efficient B-tree layer implementation for flash-memory storage systems , 2007 .

[23]  Qi Zhang,et al.  Optimizing translation information management in NAND flash memory storage systems , 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

[24]  Huazhong Yang,et al.  A compression-based area-efficient recovery architecture for nonvolatile processors , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).