A reconfiguration algorithm for wafer-scale integration of systolic arrays

Abstract A major problem with assembling a large system of cells on a single wafer is that some of the elements are likely to be defective. Hence a practical procedure for integrating wafer scale systems should be fault-tolerant, that is it should have the ability to configure network arounf fault. The paper presents a reconfiguration algorithm for WSI of two dimensional array. Characteristic of the algorithm is minimization of the path lengths and hence the interconnection delays between the cells of the array.

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