An Efficient Viterbi Decoder Implementation for the ZSP 500 DSP Core

This paper describes an efficient implementation of the Viterbi decoding algorithm on the ZSP500 digital signal processor (DSP) core. It starts with an introduction to convolutional coding and Viterbi decoding as a method of forward error correction in communication systems. An introduction to the ZSP500 architecture is followed by a description of special instructions for performing the Trellis butterfly. Examples of branch metrics calculation, Trellis butterfly, and trace-back are given. Performance benchmarks for the Viterbi algorithm running on ZSP500 are presented. Finally, the use of a Viterbi coprocessor for the task of state metric update and trace-back is discussed.