Compiler-Directed Dynamic Voltage Scaling Based on Program Regions

This paper discusses the design and implementation of the first compiler that optimizes programs for power and energy using dynamic voltage scaling. The compiler identifies program regions where the CPU can be slowed down without resulting in a significant overall performance loss. For such regions the lowest CPU voltage is selected that operates correctly under the reduced clock frequency. Our trace-based compiler prototype uses the SUIF2 compiler infrastructure. For the SPECfp95 benchmark, simulation results show energy savings of up to 24% with performance penalties of less than 2.7%.

[1]  Rajesh Gupta,et al.  Profile-based dynamic voltage scheduling using program checkpoints , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[2]  James R. Goodman,et al.  Hardware techniques to improve the performance of the processor/memory interface , 1998 .

[3]  Scott Shenker,et al.  Scheduling for reduced CPU energy , 1994, OSDI '94.

[4]  Kiyoung Choi,et al.  Power optimization of real-time embedded systems on variable speed processors , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[5]  Hiroto Yasuura,et al.  Real-time task scheduling for a variable voltage processor , 1999, Proceedings 12th International Symposium on System Synthesis.

[6]  Krishnendu Chakrabarty,et al.  Investigating the effect of voltage-switching on low-energy task scheduling in hard real-time systems , 2001, ASP-DAC '01.

[7]  Hal Wasserman,et al.  Comparing algorithm for dynamic speed-setting of a low-power CPU , 1995, MobiCom '95.

[8]  Mahmut T. Kandemir,et al.  Influence of compiler optimizations on system power , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[9]  Rami Melhem,et al.  Toward the placement of power management points in real-time applications , 2003 .

[10]  Lizy K. John,et al.  Is Compiling for Performance — Compiling for Power? , 2001 .

[11]  Michael S. Hsiao,et al.  Compiler-directed dynamic voltage/frequency scheduling for energy reduction in microprocessors , 2001, ISLPED '01.

[12]  F. Frances Yao,et al.  A scheduling model for reduced CPU energy , 1995, Proceedings of IEEE 36th Annual Foundations of Computer Science.

[13]  Anil Seth,et al.  Algorithms for energy optimization using processor instructions , 2001, CASES '01.

[14]  Michael S. Hsiao,et al.  Compiler-Directed Dynamic Frequency and Voltage Scheduling , 2000, PACS.

[15]  Dongkun Shin,et al.  Intra-Task Voltage Scheduling for Low-Energy, Hard Real-Time Applications , 2001, IEEE Des. Test Comput..

[16]  Hiroto Yasuura,et al.  Voltage scheduling problem for dynamically variable voltage processors , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[17]  Ulrich Kremer,et al.  Dynamic Voltage and Frequency Scaling for Scientific Applications , 2001, LCPC.

[18]  Trevor Mudge.  Power: A First Class Design Constraint for Future Architecture and Automation , 2000, HiPC.

[19]  Dirk Grunwald,et al.  Using IPC Variation in Workloads with Externally Specified R ates to Reduce Power Consumption , 2000 .

[20]  Diana Marculescu.  On the Use of Microarchitecture-Driven Dynamic Voltage Scaling , 2000 .

[21]  Guang R. Gao,et al.  Power and Energy Impact by Loop Transformations , 2000 .

[22]  Christopher J. Hughes,et al.  Saving energy with architectural and frequency adaptations for multimedia applications , 2001, Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture. MICRO-34.

[23]  Thomas D. Burd,et al.  Voltage scheduling in the IpARM microprocessor system , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[24]  Chaitali Chakrabarti,et al.  Variable voltage task scheduling for minimizing energy or minimizing power , 2000, 2000 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.00CH37100).

[25]  Todd M. Austin,et al.  The SimpleScalar tool set, version 2.0 , 1997, CARN.

[26]  T. Sakurai,et al.  Run-time voltage hopping for low-power real-time systems , 2000, Proceedings 37th Design Automation Conference.

[27]  Rami Melhem,et al.  Adapting Processor Supply Voltage to Instruction-Level Parallelism , 2001 .

[28]  Daniel Moss,et al.  Compiler-assisted dynamic power-aware scheduling for real-time applications , 2000 .

[29]  Thomas D. Burd,et al.  Design issues for Dynamic Voltage Scaling , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[30]  Majid Sarrafzadeh,et al.  Variable voltage scheduling , 1995, ISLPED '95.

[31]  Miodrag Potkonjak,et al.  Power optimization of variable-voltage core-based systems , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[32]  Johan Pouwelse,et al.  Dynamic voltage scaling on a low-power microprocessor , 2001, MobiCom '01.

[33]  Anantha Chandrakasan,et al.  Dynamic voltage scheduling using adaptive filtering of workload traces , 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

[34]  R. Brodersen,et al.  Voltage Scheduling in the lpARM Microprocessor System , 2000 .

[35]  Mary Jane Irwin,et al.  Low Power Design: From Soup to Nuts , 2000 .