A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller

This RISC microprocessor is a new, high-performance, PowerPC microprocessor designed specifically for the mobile and high volume desktop personal computer markets. It is an advanced superscalar design with six execution units, aggressive upstream branch processing, out-of-order instruction execution, and a tightly integrated "backside" L2 cache. This dual-issue engine has a four-stage pipeline with dual 32-kB eight-way set-associative L1 caches and an integrated L2 controller with on-chip L2 tag supporting up to 1 MB of external SRAM. A thermal assist unit and an instruction cache throttling mechanism are included for thermal management in mobile applications. A 60X system bus and L2 interface speeds of 100 and 250 MHz are achieved, respectively. This microprocessor achieves workstation class performance (estimated 10 SPECint95 and 9 SPECfp95) while only dissipating 5 W at 250 MHz. The 6.35-million transistor 66.5-mm/sup 2/ die is fabricated in a 2.5-V, 0.3-/spl mu/m, five-layer metal CMOS process.

[1]  Kenneth C. Yeager,et al.  200-MHz superscalar RISC microprocessor , 1996, IEEE J. Solid State Circuits.

[2]  Steven H. Voldman,et al.  Analysis of snubber-clamped diode-string mixed voltage interface ESD protection network for advanced microprocessors☆ , 1996 .

[3]  Brad Burgess,et al.  A G3 PowerPC/sup TM/ superscalar low-power microprocessor , 1997, Proceedings IEEE COMPCON 97. Digest of Papers.

[4]  Alvarez,et al.  A CMOS Temperature Sensor For PowerPC RISC Microprocessors , 1997, Symposium 1997 on VLSI Circuits.

[5]  C. Nicoletta,et al.  A 250 MHz 5 W RISC microprocessor with on-chip L2 cache controller , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[6]  H. Sanchez,et al.  A 200 MHz 2.5 V 4 W superscalar RISC microprocessor , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[7]  Mike Alexander,et al.  Thermal management system for high performance PowerPC/sup TM/ microprocessors , 1997, Proceedings IEEE COMPCON 97. Digest of Papers.

[8]  Hector Sanchez,et al.  A 2.2 W, 80 MHz superscalar RISC microprocessor , 1994 .

[9]  Alan Jay Smith,et al.  Branch Prediction Strategies and Branch Target Buffer Design , 1995, Computer.

[10]  Mike Alexander,et al.  A scalable resistor-less PLL design for PowerPC/sup TM/ microprocessors , 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.