A novel tunnel FET design through hybrid modulation with optimized subthreshold characteristics and high drive capability

Dear editor, As CMOS technology scaling down, the reduction of supply voltage and power consumption becomes extremely difficult due to the subthreshold swing (SS) limitation (60 mV/dec) at room temperature. Tunnel FET (TFET) with band-to-band tunneling (BTBT) mechanism is regarded as one of the most promising emerging low-power devices due to its sub-60 mV/dec SS and ultra-low off-current (IOFF), especially for Si TFET [1–4]. To date, a lot of research and efforts have been made on optimizing the subthreshold characteristics of TFETs. Since the minimum subthreshold swing (SSmin) for TFET is determined by the electric field at tunnel junction when BTBT just turns on, by the novel device designs or the process optimization, TFETs with sub-60mV/dec SSmin have already been experimentally demonstrated [5–7]. However, the SS tends to degrade with the increasing VGS for traditional TFET, which is found to be fundamentally caused by the degraded BTBT generation rate increment with increasing gate voltage [8]. Hence, the most reported TFETs can only achieve steep SS within low drive current level, which may induce the large average SS (SSavg) and also low drive capability. Therefore, device optimization strategy of TFET for simultaneously achieving the steep SSmin and suppressing SS degradation is in ample necessity for TFETs. In this study, a novel junction-modulated hetero-layer TFET (JHL-TFET) is proposed and investigated. Based on the hybrid effect of adaptive bandgap engineering and junction depletedmodulation, compared with traditional TFET, JHL-TFET can achieve the steeper SSmin and the suppressed SS degradation behavior simultaneously. The device performance of JHL-TFET has been comprehensively studied to evaluate its potential for ultra-low application. Device structure and operation principle. Figure 1(a) gives the schematic and sectional view of the proposed JHL-TFET. Compared with traditional TFET, the JHL-TFET features a stripedshaped gate stretched into the stacked source region with relatively larger bandgap material as the upper layer and relatively smaller bandgap material as the underlying layer. The thicknesses of the upper layer and underlying layer are defined as Tupper and Tunderlying, respectively. Besides, the large bandgap material is also used as the channel and drain materials to ensure low off-current. The length of the striped gate stretched into the source region is defined as Lf and the width of the striped gate is defined as Wf . By using Synopsys TCAD Sentaurus simulation tools, device simulation was carried out to investi-