Testing of critical paths for delay faults
暂无分享,去创建一个
[1] Kwang-Ting Cheng,et al. Identification and test generation for primitive faults , 1996, Proceedings International Test Conference 1996. Test and Design Validity.
[2] D. M. H. Walker,et al. Test generation for global delay faults , 1996, Proceedings International Test Conference 1996. Test and Design Validity.
[3] Janak H. Patel,et al. Enhanced delay defect coverage with path-segments , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).
[4] Janak H. Patel,et al. Segment delay faults: a new fault model , 1996, Proceedings of 14th VLSI Test Symposium.
[5] Kwang-Ting Cheng,et al. Path selection for delay testing of deep sub-micron devices using statistical performance sensitivity analysis , 2000, Proceedings 18th IEEE VLSI Test Symposium.
[6] Kwang-Ting Cheng,et al. Classification and identification of nonrobust untestable path delay faults , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[7] Kwang-Ting Cheng,et al. Delay testing for non-robust untestable circuits , 1993, Proceedings of IEEE International Test Conference - (ITC).
[8] Robert K. Brayton,et al. Delay Fault Coverage and Performance Tradeoffs , 1993, 30th ACM/IEEE Design Automation Conference.
[9] Sudhakar M. Reddy,et al. On Delay Fault Testing in Logic Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[10] Seiichiro Tani,et al. Efficient Path Selection for Delay Testing Based on Path Clustering , 1999, J. Electron. Test..
[11] Michael Pabst,et al. RESIST: a recursive test pattern generation algorithm for path delay faults , 1994, EURO-DAC '94.
[12] Gordon L. Smith,et al. Model for Delay Faults Based upon Paths , 1985, ITC.
[13] Sudhakar M. Reddy,et al. Fast Identification of Robust Dependent Path Delay Faults , 1995, 32nd Design Automation Conference.
[14] S. Sahni,et al. On path selection in combinational logic circuits , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..
[15] Premachandran R. Menon,et al. Synthesis of Delay-Verifiable Combinational Circuits , 1995, IEEE Trans. Computers.
[16] Haluk Konuk. On invalidation mechanisms for non-robust delay tests , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).