Stacked-Nanowire and FinFET Transistors: Guidelines for the 7nm Node

This study, based on 3D TCAD simulation, suggests innovative guidelines for benchmarking performances of stacked-nanowires and FinFET architectures. Immunity to short-channel effects (SCE), parasitic capacitances, and switching delays are evaluated. Thin and wide gate-allaround (GAA) stacked-nanowires are found to be the most promising devices for the 7nm node.