A heterogeneous multi-core SoC for mixed criticality industrial automation systems

The paper introduces a new multi-core SoC platform designed for industrial automation applications with mixed criticality. The applications are written in SystemJ language. The multi-core platform consisting of three different types of cores is implemented in a SoC that contains a standard dual-core ARM and a FPGA, which is used to run the critical part of the system. The platform is fully customizable in terms of number and types of cores to the needs of the application. An industrial automation case study is used to demonstrate the use and performance of the multi-core SoC.

[1]  Zoran Salcic,et al.  A Time Predictable Heterogeneous Multicore Processor for Hard Real-time GALS Programs , 2016 .

[2]  Zoran A. Salcic,et al.  SystemJ: A GALS language for system level design , 2010, Comput. Lang. Syst. Struct..

[3]  Roman Obermaisser,et al.  Architectures for mixed-criticality systems based on networked multi-core chips , 2014, Proceedings of the 2014 IEEE Emerging Technology and Factory Automation (ETFA).

[4]  Joël Goossens,et al.  Schedulability and sensitivity analysis of multiple criticality tasks with fixed-priorities , 2009, Real-Time Systems.

[5]  Rolf Ernst,et al.  IDAMC: A NoC for mixed criticality systems , 2013, 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications.

[6]  Lothar Thiele,et al.  Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources , 2015, Real-Time Systems.

[7]  Zoran A. Salcic,et al.  Scheduling Globally Asynchronous Locally Synchronous Programs for Guaranteed Response Times , 2015, TODE.

[8]  Michael Paulitsch,et al.  Mixed-Criticality Embedded Systems -- A Balance Ensuring Partitioning and Performance , 2015, 2015 Euromicro Conference on Digital System Design.

[9]  Martin Schoeberl,et al.  A Java processor architecture for embedded real-time systems , 2008, J. Syst. Archit..

[10]  Zoran A. Salcic,et al.  FPGA-based Mixed-Criticality Execution Platform for SystemJ and the Internet of Industrial Things , 2015, 2015 IEEE 18th International Symposium on Real-Time Distributed Computing.

[11]  Robert I. Davis,et al.  Mixed Criticality Systems - A Review , 2015 .