Booth Folding Encoding for High Performance
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[1] D. D. Caro,et al. Parallel squarer using Booth-folding technique , 2001 .
[2] Atsuki Inoue,et al. A 4.1-ns Compact 54 54-b Multiplier Utilizing Sign-Select Booth Encoders , 1997 .
[3] F. Elguibaly,et al. A fast parallel multiplier-accumulator using the modified Booth algorithm , 2000 .
[4] Chein-Wei Jen,et al. High-Speed Booth Encoded Parallel Multiplier Design , 2000, IEEE Trans. Computers.
[5] Davide De Caro,et al. New design of squarer circuits using Booth encoding and folding techniques , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).
[6] Neil Weste,et al. Principles of CMOS VLSI Design , 1985 .
[7] Rajeev Jain,et al. An integrated circuit design for pruned tree-search vector quantization encoding with an off-chip controller , 1992, IEEE Trans. Circuits Syst. Video Technol..
[8] John G. Proakis,et al. Digital Communications , 1983 .
[9] Ganesh Gopalakrishnan,et al. A fast parallel squarer based on divide-and-conquer , 1997 .
[10] Jalil Fadavi-Ardekani. M×N Booth encoded multiplier generator using optimized Wallace trees , 1993, IEEE Trans. Very Large Scale Integr. Syst..
[11] J. Pihl,et al. A multiplier and squarer generator for high performance DSP applications , 1996, Proceedings of the 39th Midwest Symposium on Circuits and Systems.
[12] Earl E. Swartzlander,et al. Reduced area multipliers , 1993, Proceedings of International Conference on Application Specific Array Processors (ASAP '93).
[13] Fengqi Yu,et al. Multirate digital squarer architectures , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).
[14] Ravi Kumar Kolagotla,et al. VLSI implementation of 350 MHz 0.35 /spl mu/m 8 bit merged squarer , 1998 .