论文信息 - High speed radix-16 design of a scalable Montgomery multiplier

High speed radix-16 design of a scalable Montgomery multiplier

This paper describes an improved version of the Tenca-Todorov-Koc word based radix-8 Montgomery multiplier. It uses radix-16 for fast without adding any hardware, and adjusting the data-path to get shorter critical path, and requires half of FIFO memory. This design is reconfigurable to accept any input precision as the Tenca-Todorov-Koc's design. An ASIC implementation in 0.25 mum CMOS standard cell technology can perform 2048-bit modular exponentiation in 28ms under 125MHz clock period

[1] P. L. Montgomery. Modular multiplication without trial division , 1985 .

[2] Çetin Kaya Koç,et al. A Scalable Architecture for Modular Multiplication Based on Montgomery's Algorithm , 2003, IEEE Trans. Computers.

[3] Adi Shamir,et al. A method for obtaining digital signatures and public-key cryptosystems , 1978, CACM.

[4] Andrew D. Booth,et al. A SIGNED BINARY MULTIPLICATION TECHNIQUE , 1951 .

[5] Georgi Todorov,et al. ASIC design, implementation and anaylsis of a scalable high-radix Montgomery Multiplier , 2000 .

[6] Çetin Kaya Koç,et al. A Scalable Architecture for Montgomery Multiplication , 1999, CHES.

[7] Çetin Kaya Koç,et al. High-Radix Design of a Scalable Modular Multiplier , 2001, CHES.

[8] Tolga Acar,et al. Analyzing and comparing Montgomery multiplication algorithms , 1996, IEEE Micro.