ATPD: an automatic test pattern generator for path delay faults

In this paper we present an efficient test pattern generator for robust path delay faults, which we call ATPD. Our CAD tool detects much faster more robust path delay faults than any other existing nonenumerative approach. ATPD generates patterns for a non necessarily polynomial number of path delay faults. The nature of the problem indicates that for a test generator to be efficient it must count nonenumeratively the additional delay paths detected by each generated pair of patterns. ATPD generates each pair of patterns and determines the number of paths covered in a novel way that combines these two phases effectively.

[1]  Vishwani D. Agrawal,et al.  Energy minimization based delay testing , 1992, [1992] Proceedings The European Conference on Design Automation.

[2]  L. H. Goldstein,et al.  Controllability/observability analysis of digital circuits , 1978 .

[3]  Sudhakar M. Reddy,et al.  Fast Identification of Robust Dependent Path Delay Faults , 1995, 32nd Design Automation Conference.

[4]  Irith Pomeranz,et al.  Test generation for path delay faults based on learning , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[5]  Dhiraj K. Pradhan,et al.  A method to derive compact test sets for path delay faults in combinational circuits , 1993, Proceedings of IEEE International Test Conference - (ITC).

[6]  Spyros Tragoudas,et al.  Delay considerations in testing and synthesis of integrated circuits , 1996 .

[7]  Sudhakar M. Reddy,et al.  On the design of robust multiple fault testable CMOS combinational logic circuits , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[8]  Kwang-Ting Cheng,et al.  Test Generation for Path Delay Faults , 1998 .

[9]  Michael H. Schulz,et al.  Advanced automatic test pattern generation techniques for path delay faults , 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[10]  Vishwani D. Agrawal,et al.  An Efficient Path Delay Fault Coverage Estimator , 1994, 31st Design Automation Conference.

[11]  Yashwant K. Malaiya,et al.  Modeling and Testing for Timing Faults in Synchronous Sequential Circuits , 1984, IEEE Design & Test of Computers.

[12]  Kwang-Ting Cheng,et al.  Generation of High Quality Non-Robust Tests for Path Delay Faults , 1994, 31st Design Automation Conference.

[13]  S. Reddy,et al.  Synthesis of combinational logic circuits for path delay fault testability , 1990, IEEE International Symposium on Circuits and Systems.

[14]  Eugene L. Lawler,et al.  The recognition of Series Parallel digraphs , 1979, SIAM J. Comput..

[15]  Irith Pomeranz,et al.  An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  John J. Shedletsky,et al.  An Experimental Delay Test Generator for LSI Logic , 1980, IEEE Transactions on Computers.

[17]  M. Ray Mercer,et al.  The interdependence between delay-optimization of synthesized networks and testing , 1991, 28th ACM/IEEE Design Automation Conference.

[18]  S. Reddy,et al.  On the design of robust multiple fault testable CMOS combinational logic circuits , 1988, ICCAD 1988.

[19]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[20]  Irith Pomeranz,et al.  NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits , 1993, 30th ACM/IEEE Design Automation Conference.

[21]  Janak H. Patel,et al.  Improving accuracy in path delay fault coverage estimation , 1996, Proceedings of 9th International Conference on VLSI Design.

[22]  Irith Pomeranz,et al.  NEST: a nonenumerative test generation method for path delay faults in combinational circuits , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[23]  Soumitra Bose,et al.  Generation of compact delay tests by multiple path activation , 1993, Proceedings of IEEE International Test Conference - (ITC).

[24]  S. Sahni,et al.  On path selection in combinational logic circuits , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[25]  Yashwant K. Malaiya,et al.  Testing for Timing Faults in Synchronous Sequential Integrated Circuits , 1983, International Test Conference.

[26]  Kaushik Roy,et al.  Synthesis of delay fault testable combinational logic , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[27]  Srinivas Devadas,et al.  Necessary and sufficient conditions for robust delay-fault testability of combinational logic circuits , 1990 .

[28]  Robert K. Brayton,et al.  Equivalence of robust delay-fault and single stuck-fault test generation , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[29]  Sudhakar M. Reddy,et al.  On Delay Fault Testing in Logic Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.