Study and Design of Low Power Universal Differential Current Conveyor

In this paper very low power CMOS universal differential difference current conveyor is designed. This is regarded as current mode circuits can be used for wireless communication. The gain, 3db bandwidth ,unity gain bandwidth, slew rate and phase margin at non inverting terminal was calculated as of 32.33dB, 781MHz, 24 GHz, 934V/ms and 47 degree. The gain, 3db bandwidth ,unity gain bandwidth, slew rate and phase margin at inverting terminal was calculated as of 30dB, 756MHz, 15.3 GHz, 934V/ms and 32.4 degree .The circuit was simulated using Cadence analog and digital design tools. The used technology is gpdk 45nm. Keywordsamplifiers (OP-AMPs), Current conveyor (CCII), Differential difference current conveyor (DDCC), Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOS).

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