VLSI Implementation of an Adaptive Edge-Enhanced Image Scalar for Real-Time Multimedia Applications

In this paper, a low-complexity adaptive edge-enhanced algorithm is proposed for the implementation of 2-D image scaling applications. The proposed novel algorithm consists of a linear space-variant edge detector, a low complexity sharpening spatial filter, and a simplified bilinear interpolation. The edge detector is designed to discover the image edges by a low-cost edge-catching technique. The sharpening spatial filter is added as a prefilter to reduce the blurring effect produced by the bilinear interpolation. Furthermore, an adaptive technology is used to enhance the effect of the edge detector by adaptively selecting the input pixels of the bilinear interpolation. In addition, an algebraic manipulation and a hardware sharing techniques are used to simplify bilinear interpolation, which efficiently reduces the computing resources and silicon area in very large scale integration (VLSI) circuits. By adding eight 8-bit registers as a register bank, this design can process streaming data directly and requires only a one-line-buffer memory. The VLSI architecture of this paper contains 6.67-K gate counts and achieves about 280-MHz processing rate by using the TSMC 0.13-um CMOS process. Compared with previous low-complexity techniques, this paper performs with better quality, higher performance, less memory requirements, and lower hardware cost than other image scaling methods.