Prefetching on the Cray-T3E

In many parallel applications, network latency causes a dramatic loss in processor utilization. This paper examines software controlled access pipelining (SCAP) as a technique for hiding network latency. An analytic model of SCAP describes basic operation techniques and predicts performance. Results are validated with benchmarks on the Cray-T3E. They show vectorized version of SCAP (V-SCAP) to be at least as fast as the highly optimized shared memory system functions. SCAP on the Cray-T3E improves performance compared to a blocking execution between 35% and 900%, while V-SCAP performs better with a factor of 2.1 to 62. SCAP achieves a performance speed-up against HPF between 48% to a factor of 9.2 dependent on the data access pattern. It also performs well on irregular access patterns which are not, supported by the standard library.

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