Conclusions and Related Work

In this thesis we have presented a partitioned approach to wavelet based image compression and its application to image encoders using programmable hardware. We have developed an efficient FPGA architecture of the state of the art image codec SPIHT, which is comparable to the original software solution in terms of visual quality. We have achieved clock rates of 40MHz for our FPGA implementations. Note that our VHDL designs were synthesized without manual optimizations. All basic memory and arithmetic modules were generated with Xilinx tools. We could improve the compression time of 512 × 512 × 8 bit greyscale images by a factor of 10 in comparison to an AMD 1GHz Athlon processor. The optional arithmetic coder compresses the modified SPIHT output by further 2 to 4 percent. It is remarkable, that the compression ratio is always improved, in the lossless as well as in the lossy case. The main contribution is that we have proposed image encoder suitable for low cost programmable hardware devices with minimal internal memory requirements. This method outperform the recently published algorithm of Wheeler and Pearlman SPIHT Image Compression without Lists[WP00] with respect to the affordable memory. In the following we will introduced the upcoming new JPEG2000 standard, which is also wavelet based, but is not premised on an embedded zerotree wavelet encoder. Afterwards, we will balance the advantages and disadvantages of our approach to the proposed method in the JPEG2000 standard. It will become apparent, that there are some marked similarities to our partitioned approach. We emphasize that both developments were done independently of each other. Note, that until now to our knowledge no JPEG2000 encoder ASIC (application specific integrated circuit) is available. First intelligent property cores for JPEG2000 codecs are offered by Amphion Semiconductor Ltd. and inSilicon Corporation in 2002 [Amp02], [inS02].