Role of Defects in the Reliability of HfO2/Si-Based Spacer Dielectric Stacks for Local Interconnects

MIM planar capacitors with different spacer dielectrics (SiN, SiCO and SiCBN) of varying thickness deposited on a 2nm Hf02 gate dielectric, were fabricated to investigate the gate/spacer stack intrinsic electrical reliability performance. The polarity dependent leakage current of gate/spacer dielectric stacks is understood by employing band diagram analyses and simulations using the Ginestra™ software. The asymmetrical J-E characteristic of the Hf02/SiN dielectric stack is attributed to the presence of a high defect density in the Hf02/SiN interface region originating from the deposition process. On the other hand, the higher as-grown defect density in SiCO and SiCBN results in a symmetrical J-E characteristic. A low defect generation efficiency in the thin SiN stacks has been demonstrated using stress induced leakage current and charge to breakdown studies. The underlying mechanisms can be linked to a change in degradation mechanism from electronic excitation to electron induced vibrational excitation, which is valid for low defect density dielectric systems. To ensure low leakage currents and robust dielectric breakdown characteristics for ultra-thin spacer layers below 5nm, it is important to control defect densities below 1019cm−3ev−1in the film.