Pre-bond Testing of the Silicon Interposer

In order to minimize the yield loss results from the stacking of good dies on a defective interposer, it is necessary to test the interposer before die stacking.

[1]  David S. Johnson,et al.  Some Simplified NP-Complete Graph Problems , 1976, Theor. Comput. Sci..

[2]  Paul Wagner,et al.  INTERCONNECT TESTING WITH BOUNDARY SCAN , 1987 .

[3]  Y. Kobayashi,et al.  A Novel Cu Electrical Fuse Structure and Blowing Scheme Utilizing Crack-Assisted Mode for 90-45nm-Node and Beyond , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[4]  D. West.  Introduction to Graph Theory , 1995 .

[5]  T. Kurihara,et al.  A Silicon interposer BGA package with Cu-filled TSV and multi-layer Cu-plating interconnect , 2008, 2008 58th Electronic Components and Technology Conference.

[6]  Katherine Shu-Min Li,et al.  Optimized Pre-bond Test Methodology for Silicon Interposer Testing , 2014, 2014 IEEE 23rd Asian Test Symposium.

[7]  Siegfried Selberherr,et al.  Electromigration failure in a copper dual-damascene structure with a through silicon via , 2012, Microelectron. Reliab..

[8]  Erik Jan Marinissen,et al.  Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base , 2011, 2011 IEEE International Test Conference.

[9]  H.. Suto,et al.  Systematic Study of the Dopant-Dependent Properties of Electrically Programmable Fuses With Silicided Poly-Si Links Through a Series of $I$– $V$ Measurements , 2007, IEEE Transactions on Device and Materials Reliability.

[10]  B. Banijamali,et al.  Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA , 2011, Electronic Components and Technology Conference.

[11]  Jeongho Cho,et al.  Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study , 2013, 2013 IEEE International Test Conference (ITC).

[12]  Shi-Yu Huang,et al.  Oscillation-Based Prebond TSV Test , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  S.K. Iyer,et al.  Electrically programmable fuse (eFUSE) using electromigration in silicides , 2002, IEEE Electron Device Letters.

[14]  Patrick Dorsey.  Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency , 2010 .

[15]  A. Ono,et al.  A Novel Via-fuse Technology Featuring Highly Stable Blow Operation with Large On-off Ratio for 32nm Node and Beyond , 2007, 2007 IEEE International Electron Devices Meeting.

[16]  Rahul Agarwal,et al.  Device performance analysis on 20nm technology thin wafers in a 3D package , 2015, 2015 IEEE International Reliability Physics Symposium.

[17]  T. Kurihara,et al.  Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring , 2008, 2008 58th Electronic Components and Technology Conference.